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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: Moore’s law
Heterogeneous SoC design gets its own foundation backed by heavy hitters. Good things sure to follow
I am an unabashed advocate of heterogeneous SoC design. Have been for decades. It’s a system-level design approach that lacks the elegance and academic symmetry of homogeneous processing in exchange for a more efficient, bare-metal, hard-core approach to system design … Continue reading
Posted in ARM, EDA360, ESL, Firmware, SoC, SoC Realization, System Realization
Tagged AMD, ARM, HSA Foundation, ImaginationTechnologies, MediaTek, Moore's law, Texas Instruments
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Moore’s Law: Wanted, Dead or Alive
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading
ISQED: Why does a trailing-edge digital IC process = a leading-edge analog IC process? TI’s Dr. Venu Menon lays bare the secrets of the analog IC business
“What can you do with bits?” asked Dr. Venu Menon, VP of Analog Technology Development at Texas Instruments at the beginning of his keynote talk at last week’s ISQED. Then he answered his own question: “Nothing without analog,” because analog … Continue reading
3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!
Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading
Posted in 10nm, 14nm, 2.5D, 3D, CDNLive!, EDA360, Packaging, Silicon Realization, SoC, SoC Realization
Tagged 2.5D, 3D, Cadence, Moore's law, TSMC
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What can 20MW Exascale computers teach us about SoC Realization?
I regularly write about Deepak Sekar’s blogs and his latest entry about a talk given by NVIDIA’s Chief Scientist Bill Dally is causing me to quote from Sekar’s blog once again. Sekar is MonolithIC 3D’s Chief Scientist, so I suppose … Continue reading
Posted in ARM, Cortex-A7, EDA360, SoC, SoC Realization, System Realization
Tagged Bill Dally, Exascale computing, Moore's law, Multi-core processor, Nvidia, Sekar
2 Comments
Processor Wars: NVIDIA reveals a phantom fifth ARM Cortex-A9 processor core in Kal-El mobile processor IC. Guess why it’s there?
NVIDIA has extended the path to many-core design by publishing a White Paper that reveals the existence of a fifth ARM Cortex-A9 processor core in the company’s previously discussed Kal-El mobile processor. This fifth processor core implements what the company … Continue reading
Posted in Android, ARM, EDA360, Honeycomb, IP, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Dennard Scaling, DVFS, Kal-El, Moore's law, Nvidia
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