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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: Multiple patterning
5-minute, 20nm Q&A. All you need to know in 5 minutes.
What are the key advantages of moving to 20nm? There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA). Essentially, this is a “next-node” answer, which is still as … Continue reading
Posted in 20nm, Silicon Realization, SoC, SoC Realization
Tagged 20nm, LDE, Multiple patterning, PPA
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20nm design: What have we learned so far?
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design
Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading
Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization
Tagged Bipolar, CMOS, Extreme ultraviolet, FinFET, Gary Patton, IBM, Multiple patterning, TriGate
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FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence
The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading
Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Cadence, Double Patterning, Multiple patterning, Samsung, Webinar
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