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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- The DDR4 SDRAM spec and SoC design. What do we know now?
- ARM adds ARM Cortex-A15 and Cortex-R5 models to Fast Models 6.1 release, making these cores immediately available to System Realization teams
- Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
- Friday Video: How the iPhone saved a Corning glass factory in Harrodsburg, Kentucky
- Friday Video: Engineering humor from Don McMillan, the chip designer turned professional comedian
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Tag Archives: OSCI
Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading
Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM
Tagged Accellera, EDA, IEEE 1666, OSCI, SoC Realization, SystemC, TLM
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OSCI and Accelera merger: And now the rest of the story courtesy of Stan Krolikoski
Accelera and OSCI (the SystemC standardization guys) announced their intent to merge this last week. Interoperability standards at multiple levels are important, so this is indeed an important announcement. Stan Krolikoski, Group Director for EDA/IP Standards & Interoperability at Cadence, … Continue reading
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