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Top Posts
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Friday Video: Circuit simulation app for Android. SPICE for $10, runs in your hand? Well, almost.
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
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Tag Archives: OSCI
Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading
Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM
Tagged Accellera, EDA, IEEE 1666, OSCI, SoC Realization, SystemC, TLM
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OSCI and Accelera merger: And now the rest of the story courtesy of Stan Krolikoski
Accelera and OSCI (the SystemC standardization guys) announced their intent to merge this last week. Interoperability standards at multiple levels are important, so this is indeed an important announcement. Stan Krolikoski, Group Director for EDA/IP Standards & Interoperability at Cadence, … Continue reading
