Tag Archives: Panasonic

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

Posted in 2.5D, 3D, EDA360, imec, SoC, SoC Realization | Tagged , , , , , , , , , , , , , , , | Leave a comment

3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises

Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading

Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV | Tagged , , , , , , , , , , | 1 Comment