Tag Archives: PCIe Gen 3

Detailed analysis of the Cadence PCIe Gen 3 IP and VIP launch from SemiWiki’s Eric Esteve

A bit of analysis and a little history goes a long way to fleshing out the product announcement of Cadence’s PCIe Gen 3 IP and VIP offerings. This just-published analysis by SemiWiki’s Eric Esteve provides both.

Posted in EDA360, IP, SoC Realization, Verification | Tagged , , | Leave a comment