Tag Archives: PCIe

Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence

On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading

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Posted in EDA360, SoC Realization, System Realization, Verification, VIP | Tagged , , , , | Leave a comment

AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design

Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display … Continue reading

Posted in 32nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

Fast serial I/O—What’s its future in the embedded world?

Tom Williams, Editor-in-Chief of RTC Magazine, recently published an editorial titled “Fast Serial Interconnects— Will They Bypass Embedded or Bring it Along?” In this editorial, Williams ponders the question of fast I/O port suitability for embedded design. He writes: “Once … Continue reading

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Detailed analysis of the Cadence PCIe Gen 3 IP and VIP launch from SemiWiki’s Eric Esteve

A bit of analysis and a little history goes a long way to fleshing out the product announcement of Cadence’s PCIe Gen 3 IP and VIP offerings. This just-published analysis by SemiWiki’s Eric Esteve provides both.

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