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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Friday Video: Circuit simulation app for Android. SPICE for $10, runs in your hand? Well, almost.
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
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Tag Archives: Renesas
3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics
Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged JEDEC, mobile phone, Renesas, SoC, Wide I/O
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