Tag Archives: Richard Goering

3D Thursday: What the Cadence purchase of signal- and power-integrity EDA toolmaker Sigrity means for 2.5D and 3D IC assembly

Richard Goering has just published an in-depth analysis in his Industry Insights blog that explains what the Cadence purchase of signal- and power-integrity EDA toolmaker Sigrity means for pcb and IC package designers. Goering quotes Brad Griffin, product marketing director … Continue reading

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This just out from DAC 2012: video interview with EDA bloggers Goering and Leibson on IP subsystems, 20nm, and more

Want to know what’s going to happen at DAC 2012? Oh, wait, that was a couple of weeks ago. Which is how long it took to get post this video of EDA bloggers Richard Goering and Steve Leibson from a … Continue reading

Posted in 20nm, 28nm, DAC, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , | Leave a comment

Are you preparing for 20nm design? This FREE On-Demand Webinar can help.

Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading

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Four Significant EDA technologies of 2011 and what they mean to your IC design team

This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading

Posted in EDA360, Silicon Realization, SoC, TLM, VIP, Virtual Prototyping | Tagged , , , , | Leave a comment