Tag Archives: RTL

Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development

In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging … Continue reading

Advertisement

Posted in EDA360, FPGA, SoC, SoC Realization | Tagged , , , | Leave a comment

Low-Power Design: Is the Problem Solved?

“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading

Posted in EDA360, IP, Low Power, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

Software development for SoCs requires “bespoke” software enablement platforms

I’ve always wanted to use the British English word “bespoke” in a blog and Cadence Group Director of Product Marketing for the System Development Suite Frank Schirrmeister has now given me that opportunity with his EDPS forecast on system-level EDA … Continue reading

Posted in EDA360, System Realization | Tagged , , , , , , , | Leave a comment

EDPS (April 5-6) in Monterey tackles “Top EDA Problems” with speakers from Broadcom, Cadence, AMD, and Synopsys

Early next month in Monterey, California, the Electronic Design Processes Symposium will take on the “Top Five EDA Problems.” For the purpose of this event, these problems would appear to be DFT (design for testability), System-Level EDA, Parallel EDA, and … Continue reading

Posted in EDA360, Silicon Realization, SoC Realization, System Realization | Tagged , , , , | Leave a comment

System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang

Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading

Posted in EDA360, FPGA prototyping, SoC, SoC Realization, System Realization, SystemC, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , , , , | 1 Comment