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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- 3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs
- Collaboration is key to making DFM work at 28nm and below
- 3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron
- Friday Video: How many hardware/software integration lessons can you absorb in 34 minutes?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- Intel’s Knut Grimsrud explains how to get another 20x improvement in SSD performance
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
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Tag Archives: Sekar
What can 20MW Exascale computers teach us about SoC Realization?
I regularly write about Deepak Sekar’s blogs and his latest entry about a talk given by NVIDIA’s Chief Scientist Bill Dally is causing me to quote from Sekar’s blog once again. Sekar is MonolithIC 3D’s Chief Scientist, so I suppose … Continue reading
Posted in ARM, Cortex-A7, EDA360, SoC, SoC Realization, System Realization
Tagged Bill Dally, Exascale computing, Moore's law, Multi-core processor, Nvidia, Sekar
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