Tag Archives: Silicon Realization

Are you preparing for 20nm design? This FREE On-Demand Webinar can help.

Posted on May 7, 2012 by

Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading →

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Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.

Posted on April 25, 2012 by

The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading →

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Power-intent methodologies: Can’t we all just get along?

Posted on February 13, 2012 by

All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading →

Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | Leave a comment