Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Download the EDA360 Vision Paper here:
Tag Archives: Silicon Realization
Are you preparing for 20nm design? This FREE On-Demand Webinar can help.
Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading
Posted in 20nm, EDA360, Silicon Realization
Tagged 20nm, ARM, Cadence, Richard Goering, Silicon Realization, TSMC
Leave a comment
Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.
The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading
Power-intent methodologies: Can’t we all just get along?
All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization
Tagged ASIC, CPF, IEEE 1801, Silicon Realization, SoC, System-on-a-chip, UPF
Leave a comment
EDA360 Insider 