Tag Archives: SoC Realization

System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang

Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading


Posted in EDA360, FPGA prototyping, SoC, SoC Realization, System Realization, SystemC, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , , , , | 1 Comment

EDA VC Jim Hogan to connect the dots between user experience and SoC Realization at EDPS in April

It’s pretty hard to go from high-level customer expectations for an end product to the definition of an SoC. If it were easy, everyone would be able to do it. You have a unique chance to hear EDA venture capitalist … Continue reading

Posted in EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0

Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading

Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM | Tagged , , , , , , | Leave a comment