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Tag Archives: ST Ericsson
3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program
ElectroIQ reports that CEA-Leti in Grenoble has just launched an Open 3D IC program to permit companies more open access to the 3D IC assembly technologies developed at the research center. Last December, CEA-Leti and ST-Ericsson made a joint presentation … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged 3D, 3D IC, CEA-Leti, micro pillar, microbump, ST Ericsson, TSV
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3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Yesterday, at the RTI 3D Conference, Pascal Vivet from CEA-Leti and Vincent Guérin from ST-Ericsson unveiled a 3D IC project that represents a real Tour de Force of cutting-edge system technology. The quest starts with a key question: “What’s the … Continue reading
Posted in 3D, ARM, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, Leti, LTE, Multicore, NoC, ST Ericsson, TSV, Wide I/O
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Would you like some ARM Cortex-A15 resources to peruse?
Thanks to LinkedIn ARM Based Group community manager Stephan Cadene, we’ve got several pointers to useful documents describing many aspects of the ARM Cortex-A15 processor core. This is all in preparation for many discussions of the ARM Cortex-A15 processor taking … Continue reading
Posted in Android, ARM, Cortex-A15, Ecosystem, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization
Tagged ARM architecture, Broadcom, Cortex-A15, Cortex-A5, Cortex-A8, Cortex-A9, Nvidia, Samsung, ST Ericsson, TechCon, Texas Instruments
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