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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- EMA Design Automation announces FootprintGen—an app for Cadence Allegro and OrCAD PCB design tools that cuts the time needed to design PCB footprint models for new components
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Friday Video: Want the basics of PCB design in 45 minutes? Dave Jones delivers yet again with a free tutorial.
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Tag Archives: stacked silicon
3D Thursday (Late): Sony to invest 80 billion Yen in stacked CMOS sensor manufacturing expansion
Quoting a corporate press release, the Web site http://www.dpreview.com reports that Sony Corp intends to invest approximately 80 billion Yen through the end of March, 2014 to expand its capacity to manufacture “stacked silicon sensors,” which are 3D IC assemblies … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization
Tagged 3D, backside illumination, Sony, stacked silicon
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