Tag Archives: SV-AMS

FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST

Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading

Posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification | Tagged , , , , , | Leave a comment