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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- AppliedMicro demos FPGA emulation of multicore server chip based on new 64-bit ARMv8 architecture
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
- More news on the asymmetric processing SoC front
- Friday Video: Xtreme Embedded Design—A fully operational, 1/6-scale Atari Star Wars Arcade machine
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- The DDR4 SDRAM spec and SoC design. What do we know now?
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Tag Archives: SV-AMS
FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST
Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading
Posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification
Tagged AMS, Analog, Mixed Signal, SV-AMS, SystemVerilog, verification
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