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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O XilinxTop Posts
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Want a peek at a possible Qualcomm 3D IC roadmap?
- 3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
- 3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- 3D Thursday: Three on 3D—papers from ISSCC
- DARPA wants a more PERFECT processing engine with a 75x improvement in GFLOPS/Watt. Want to play?
- Asymmetric, dual-core NXP LPC4300 microcontrollers split tasks between ARM Cortex-M4 and -M0 cores, cost $3.75 and up
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Tag Archives: Synopsys
You have six weeks to wait for the Semico IP Summit. What will you do until then?
Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading
Posted in EDA360, IP, SoC Realization
Tagged Advanced Micro Devices, Cadence, GlobalFoundries, Mentor Graphics, SoC, Synopsys, TSMC
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Friday Video: EDAC video of Feb 29 EDA CEO Forecast and Industry Vision Event
On leap day (Feb 29), EDAC held its annual CEO Forecast and Industry Vision event at Silicon Valley Bank in, er, Silicon Valley. Speakers included CEOs Wally Rhines (Mentor), Aart de Geus (Synopsys), Lip-Bu Tan (Cadence), and Ed Cheng (Gradient) … Continue reading
EDPS (April 5-6) in Monterey tackles “Top EDA Problems” with speakers from Broadcom, Cadence, AMD, and Synopsys
Early next month in Monterey, California, the Electronic Design Processes Symposium will take on the “Top Five EDA Problems.” For the purpose of this event, these problems would appear to be DFT (design for testability), System-Level EDA, Parallel EDA, and … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged AMD, Broadcom, Cadence, RTL, Synopsys
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Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics
Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading
Posted in 3D, Apps, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, EDA, IP, IP Integration, Lego, Low Power, Mentor Graphics, Synopsys
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“Professor” Aart de Geus gives latest Techonomics lecture on collaboration and System Realization at the Semico Summit in Scottsdale
Last week, Synopsys Chairman of the Board and CEO Aart de Geus gave a keynote at the Semico Summit in Scottsdale. His topics were “Techonomics,” collaboration, and systemic complexity. Techonomics is de Geus’ name for the fusion of technology and … Continue reading
Posted in Apps, Design Abstraction, Design Convergence, Design Intent, Ecosystem, EDA360, System Realization
Tagged Aart de Geus, Semico Summit, Synopsys
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