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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- AppliedMicro demos FPGA emulation of multicore server chip based on new 64-bit ARMv8 architecture
- Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips
- FREE DAC 2012 Exhibit 3-day passes. Limited quantity. Time-limited offer. Get ‘em NOW!
- Want to see the future of low-power SoC design? Have a look into Gary Smith’s crystal ball.
- Want a peek at a possible Qualcomm 3D IC roadmap?
- Common Platform: Why do these companies (IBM, Samsung, GLOBALFOUNDRIES) collaborate?
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- 3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: synthesis
DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping
Tagged DAC, EDA, IC design, pcb, synthesis, verification
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