Tag Archives: System-on-a-chip

How to program all of those SoC processor cores? Answers from Jim Ready. Free event, September 18.

While we can stamp out processors galore on an advanced-node SoC, programming those processors is another matter entirely. Yet “multicore” and “many-core” SoC designs are the in-vogue approach to processing performance. How to solve this dilemma? Get a glimpse of … Continue reading

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Meaty new book on Mixed-Signal SoC Design, Verification and Implementation Methodology is nearly ready

Is your current SoC project a mixed-signal design? If not, chances are good that the next one will be. That’s because there’s been an evolution in SoC design from pure digital to analog/mixed-signal (AMS) designs over the past several years … Continue reading

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Smart analog/mixed-signal IC designs are—er—smarter. Learn how to stuff a 32-bit ARM Cortex-M core into an AMS design at DAC. Lunch included

In these days of the SoC, one chip has to do it all. That means both analog and digital processing. Now you can get a first-hand look at how successful design teams have integrated ARM Cortex-M processor cores in their … Continue reading

Posted in ARM, Cortex-M0, Cortex-M4, DAC, Mixed Signal, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.

The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading

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Power-intent methodologies: Can’t we all just get along?

All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading

Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | Leave a comment