Tag Archives: SystemVerilog

Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.

You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading

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Four Significant EDA technologies of 2011 and what they mean to your IC design team

This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading

Posted in EDA360, Silicon Realization, SoC, TLM, VIP, Virtual Prototyping | Tagged , , , , | Leave a comment

FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST

Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading

Posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification | Tagged , , , , , | Leave a comment

Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20

Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading

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Grant Martin book review: “TLM-Driven Design and Verification Methodology”

My good friend Grant Martin has written a ton of books, book chapters, and articles about a wide range of EDA topics and he often reviews related books. He’s just published a review of the new book “TLM-Driven Design and … Continue reading

Posted in EDA360, Silicon Realization, SoC Realization, System Realization | Tagged , | 1 Comment