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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Between ASIC and microcontroller: It’s all about System Realization
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- What do you do when two processors just won’t do? TI’s OMAP 5 SoCs sport 4-in-hand ARM cores, IP Subsystems
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Tag Archives: SystemVerilog
Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Four Significant EDA technologies of 2011 and what they mean to your IC design team
This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading
FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST
Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading
Posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification
Tagged AMS, Analog, Mixed Signal, SV-AMS, SystemVerilog, verification
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Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading
Posted in System Realization, SystemC, UVM, Verification
Tagged Accelera, SystemC, SystemVerilog, TLM, UVM
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Grant Martin book review: “TLM-Driven Design and Verification Methodology”
My good friend Grant Martin has written a ton of books, book chapters, and articles about a wide range of EDA topics and he often reviews related books. He’s just published a review of the new book “TLM-Driven Design and … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Specman, SystemVerilog
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