Tag Archives: Tri-Gate

GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley

Posted on February 7, 2012 by sleibson2

The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading →

Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | 1 Comment

Friday Video: Intel does 22nm, 3D, and humor in one video. Who knew they had it in them?

Posted on August 5, 2011 by sleibson2
Posted in EDA360, Silicon Realization | Tagged , , , | Leave a comment

Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu

Posted on June 19, 2011 by sleibson2

Intel announced in early May that it would be using “Tri-Gate” FETs to build microprocessors at the 22nm node. (See the previous EDA360 Insider post “3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D”). Intel’s Tri-Gate transistor structures … Continue reading →

Posted in EDA360, Low Power, Silicon Realization | Tagged , , , , | 3 Comments

3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D

Posted on May 19, 2011 by sleibson2

Earlier this month, Intel announced that it will be using Tri-Gate transistors (FinFETs) to build microprocessors at the 22nm process node. The microprocessor is code-named “Ivy Bridge.” It will be a 22nm version of the company’s Sandy Bridge processor and … Continue reading →

Posted in 3D, EDA360, Low Power, Silicon Realization, SoC Realization | Tagged , , , , , , | 3 Comments