Tag Archives: Universal Verification Methodology

Four Significant EDA technologies of 2011 and what they mean to your IC design team

This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading

Posted in EDA360, Silicon Realization, SoC, TLM, VIP, Virtual Prototyping | Tagged , , , , | Leave a comment