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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- ARM adds ARM Cortex-A15 and Cortex-R5 models to Fast Models 6.1 release, making these cores immediately available to System Realization teams
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Want to see the future of low-power SoC design? Have a look into Gary Smith’s crystal ball.
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Collaboration is key to making DFM work at 28nm and below
- Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
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Tag Archives: UVM
Free Webinar. Maximize the power of UVM runtime phases to avoid common verification pitfalls.
Verification expert Kathleen Meade has authored a methodology for applying UVM runtime phases that appears in the second edition of the Cadence UVM Book. On December 7, Kathleen will present a free verification Webinar covering the following topics: Basics of … Continue reading
Posted in EDA360, SoC, SoC Realization, System Realization, Verification
Tagged runtime phase, UVC, UVM, verification
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Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading
Posted in System Realization, SystemC, UVM, Verification
Tagged Accelera, SystemC, SystemVerilog, TLM, UVM
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EDA360, verification, UVM, and the future of EDA standards
Adam Sherilog Sherer, the Cadence Incisive Product Management Director, just published a blog about his experience in calling on several existing customers to discuss UVM (The Universal Verification Methodology being developed under Accelera’s banner). (“We Want UVM 1.0! When Do … Continue reading
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