Tag Archives: Verilog

Looking for an introductory Verilog book? How’s $24.95 sound?

Posted on August 9, 2012 by

Bob Zeidman, founder and president of Zeidman Consulting, has just published the third edition of his book “Introduction to Verilog.” It was first published a dozen years ago and is based on the Verilog seminars that Zeidman has given at … Continue reading →

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Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.

Posted on June 25, 2012 by

You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading →

Posted in EDA360, SoC Realization, System Realization, Verification | Tagged , , , , , | Leave a comment

Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP

Posted on February 21, 2012 by

In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully … Continue reading →

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