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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Welcome to 3D Week: Why is 3D important? Now? The memory wall, heat, and disposable sensors
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Intel says Moore’s Law alive and well and living at 32nm
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- Friday Video: Want the basics of PCB design in 45 minutes? Dave Jones delivers yet again with a free tutorial.
- Why doesn’t your pc board work?
- Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley
- How DAC Got Started: Richard Goering interviews Kaufman Award Winner Pat Pistilli
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Tag Archives: Verilog
Looking for an introductory Verilog book? How’s $24.95 sound?
Bob Zeidman, founder and president of Zeidman Consulting, has just published the third edition of his book “Introduction to Verilog.” It was first published a dozen years ago and is based on the Verilog seminars that Zeidman has given at … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization, Verilog
Tagged Bob Zeidman, Hardware description language, Verilog, Zeidman
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Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged 100 Gigabit Ethernet, 100G, 40G, Ethernet, Gigabit Ethernet, Media Access Control, MII, PCS, PHY, SerDes, Verilog
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