Tag Archives: VIP

Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence

On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading

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10 questions to ask your verification IP (VIP) supplier

Last month, Richard Goering wrote an excellent blog post on “Best Practices for Selecting and Using Verification IP (VIP).” In this blog post, Richard listed ten questions you should make sure you can answer when selecting commercial VIP. The ten … Continue reading

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Do you know all of the essential aspects of VIP to make a good make/buy decision?

The growth of standards-based interfaces and the rapid advance in the state of the art for SoC design have created a real need for pro-quality verification IP (VIP). One interesting facet of VIP development is its parallel evolution with design … Continue reading

Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Verification, VIP | Tagged , , | 2 Comments