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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- 3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs
- Collaboration is key to making DFM work at 28nm and below
- 3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron
- Friday Video: How many hardware/software integration lessons can you absorb in 34 minutes?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- Intel’s Knut Grimsrud explains how to get another 20x improvement in SSD performance
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
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Tag Archives: Virtex 7
Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can
Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading
Posted in 2.5D, 3D, EDA360, SoC, SoC Realization, System Realization
Tagged 2.5D, 28Gbps, Altera, FPGA, software, Virtex 7, Xilinx
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3D Thursday: Is 2.5D IC assembly “buzz-worthy”?
I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading
Posted in 2.5D, 3D, Silicon Realization, SoC, SoC Realization
Tagged 2.5D, 2000T, 3D, Virtex 7, Xilinx
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3D Thursday: 3D-IC Design Tools and Services Tour Guide is just in time for DAC. You can download a copy now.
The GSA has just issued a 3D-IC tools and services guide in time for DAC. This 62-page guide provides eight pages of background info on the state of 3D assembly technology based on public information like that provided by Xilinx … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization
Tagged 2.5D, 3D, FPGA, GSA, Virtex 7, Xilinx
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3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for … Continue reading
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