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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- How DAC Got Started: Richard Goering interviews Kaufman Award Winner Pat Pistilli
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Apps define storage task, create application-specific SSD
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Tag Archives: Virtex 7
Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can
Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading
Posted in 2.5D, 3D, EDA360, SoC, SoC Realization, System Realization
Tagged 2.5D, 28Gbps, Altera, FPGA, software, Virtex 7, Xilinx
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3D Thursday: Is 2.5D IC assembly “buzz-worthy”?
I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading
Posted in 2.5D, 3D, Silicon Realization, SoC, SoC Realization
Tagged 2.5D, 2000T, 3D, Virtex 7, Xilinx
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3D Thursday: 3D-IC Design Tools and Services Tour Guide is just in time for DAC. You can download a copy now.
The GSA has just issued a 3D-IC tools and services guide in time for DAC. This 62-page guide provides eight pages of background info on the state of 3D assembly technology based on public information like that provided by Xilinx … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization
Tagged 2.5D, 3D, FPGA, GSA, Virtex 7, Xilinx
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3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for … Continue reading
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