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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Welcome to 3D Week: Why is 3D important? Now? The memory wall, heat, and disposable sensors
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Intel says Moore’s Law alive and well and living at 32nm
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- Friday Video: Want the basics of PCB design in 45 minutes? Dave Jones delivers yet again with a free tutorial.
- Why doesn’t your pc board work?
- Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley
- How DAC Got Started: Richard Goering interviews Kaufman Award Winner Pat Pistilli
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Tag Archives: Virtex
3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading
3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Virtex, Xilinx
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