Tag Archives: virtual prototyping

System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang

Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading


Posted in EDA360, FPGA prototyping, SoC, SoC Realization, System Realization, SystemC, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , , , , | 1 Comment

Interested in reading some real-world virtual prototyping experiences?

A recent article about System Realization published on the Design and Reuse site caught my eye because it has some insightful things to say about using high-level modeling to develop complex new systems. The article is by Luca Fossati of … Continue reading

Posted in ARM, EDA360, System Realization | Tagged , | Leave a comment