Tag Archives: Webinar

Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence

Posted on July 23, 2012 by

On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading →

Posted in EDA360, SoC Realization, System Realization, Verification, VIP | Tagged , , , , | Leave a comment

FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence

Posted on May 8, 2012 by

The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading →

Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

System Realization: Free Webinars. Everyone likes them.

Posted on September 30, 2010 by

EDA360 defines System Realization as the development of complete hardware/software platforms ready for applications development even before the chip is designed. Cadence offers many free Webinars—both live and archived—that you might find useful. Here are a few Webinars related to … Continue reading →

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