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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu
- Collaboration is key to making DFM work at 28nm and below
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
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Tag Archives: Webinar
Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence
On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading
Posted in EDA360, SoC Realization, System Realization, Verification, VIP
Tagged NVMe, PCIe, verification, VIP, Webinar
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FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence
The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading
Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Cadence, Double Patterning, Multiple patterning, Samsung, Webinar
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System Realization: Free Webinars. Everyone likes them.
EDA360 defines System Realization as the development of complete hardware/software platforms ready for applications development even before the chip is designed. Cadence offers many free Webinars—both live and archived—that you might find useful. Here are a few Webinars related to … Continue reading
Posted in EDA360, System Realization
Tagged ARM, Cadence, Calypto, CircuitSutra, Imperas, TSMC, Webinar, XtremeEDA
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