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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O XilinxTop Posts
- GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
- What can you do with 45nm SOI? A lot, it turns out
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- There’s a solar eclipse coming. Here’s a test shot from a Canon 60D dSLR, a Spiratone 400mm Sharpshooter, and a 2x telextender.
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu
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Tag Archives: Xilinx
3D Thursday: Hybrid Memory Cube—wide I/O only more so—gets an industry consortium
Back in August, I wrote about the 3D SDRAM assembly called the Micron Hybrid Memory Cube (HMC, see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) and I called it a … Continue reading
Posted in 3D, EDA360, Memory, Samsung, SoC Realization
Tagged Altera, HMC, HMCC, Hybrid Memory Cube, Micron, Open-Silicon, Xilinx
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The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric
It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product … Continue reading
Posted in 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Altera, Cortex-A9, FPGA, Xilinx, Zynq
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3D Thursday: Do dis-integrated circuits reside in a 3D future? Does anyone (besides me) remember Project Tinkertoy?
I recently ran into this unusual article written by Joe Fjelstad and published on the Global SMT & Packaging Web site. The article discusses the possibility of building hybrid chips using a brick-and-mortar approach as advocated by a joint paper … Continue reading
Fire lasers! An EDA360, System Realization, and SoC Realization case study with military lasers, processors, and FPGAs
Robert S Grimes’ recently published development story is a good case study in System Realization and SoC Realization. Grimes developed a quad laser control system for a high-power military application and the article he’s published in EETimes—Designing with core-based high-density … Continue reading
6-Part series of blog posts on 28nm low-power design
Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization
Tagged 28nm, FPGA, Low Power, process technology, Xilinx
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Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
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Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
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Xilinx 28nm low-power SoC design class, part 4: Power gating RAMs
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Xilinx
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Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, TSMC, Xilinx
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Xilinx 28nm low-power SoC design class, part 2: Process Technology
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, TSMC, Xilinx
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3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!
Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization
Tagged 2.5D, 3D, FPGA, Xilinx
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3D Thursday: 3D-IC Design Tools and Services Tour Guide is just in time for DAC. You can download a copy now.
The GSA has just issued a 3D-IC tools and services guide in time for DAC. This 62-page guide provides eight pages of background info on the state of 3D assembly technology based on public information like that provided by Xilinx … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization
Tagged 2.5D, 3D, FPGA, GSA, Virtex 7, Xilinx
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3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for … Continue reading
Friday video (2fer): 28nm FPGA videos from Xilinx and Altera
Recently, Xilinx announced shipping early samples of its 28nm Kintex-7 FPGAs. Now 28nm is the current bleeding-edge process node for logic processes and it’s no small feat to start shipping parts—even early engineering samples—at this node. Here’s a video of … Continue reading
Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts
Ivo Bolsens, the Xilinx CTO and Senior VP, presented a keynote at the 8th International SoC Conference a couple of weeks ago and one of the aspects of FPGA development that he discussed was Xilinx’ plan for creating large-capacity Virtex … Continue reading
