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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap
- EETimes video of Xilinx Zync EPP shows that it takes six FPGAs to emulate one EPP
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- EDA VC Jim Hogan to connect the dots between user experience and SoC Realization at EDPS in April
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
- Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)
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