EDA analyst and SemiWiki writer Paul McLellan published an article on 20nm design last week. It’s based on the Cadence White Paper on the same topic. You can see Paul’s article here. The Cadence 20nm White Paper is here.
Advertisements
Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Moore’s Law: Wanted, Dead or Alive
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
- What can you do with 45nm SOI? A lot, it turns out
- 3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work
- Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers
Download the EDA360 Vision Paper here:
Advertisements
