EDA analyst and SemiWiki writer Paul McLellan published an article on 20nm design last week. It’s based on the Cadence White Paper on the same topic. You can see Paul’s article here. The Cadence 20nm White Paper is here.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- ARM adds ARM Cortex-A15 and Cortex-R5 models to Fast Models 6.1 release, making these cores immediately available to System Realization teams
- What would you do with a 23,000-simultaneous-thread school of piranha?...asks NVIDIA
- Between ASIC and microcontroller: It’s all about System Realization
- The DDR4 SDRAM spec and SoC design. What do we know now?
- How many SSDs does it take to saturate PCIe Gen 3? Would you believe 16 drives?
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
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