Tag Archives: GlobalFoundries

Where do semiconductor foundries come from?

Posted on September 5, 2012 by sleibson2

Have you ever wondered how we got from a world solely occupied by semiconductor vendors with their own fabs to today’s hodgepodge of IDMs (independent device manufacturers, the new name for the old-style “semiconductor vendor”), fab-lite vendors, and fables vendors? … Continue reading →

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Friday Video: Luigi Capodieci, a fellow at GLOBALFOUNDRIES, talks 20nm and below, EUV, FINFETs, and the state of the foundry business

Posted on July 20, 2012 by sleibson2

Be sure to watch this excellent 13-minute interview done by Mark LePedus starring Luigi Capodieci, a fellow with GLOBALFOUNDRIES, to get a close-up-and-personal look at the state of the foundry business (it’s not dying), 20nm design, EUV in the wings, … Continue reading →

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3D Thursday: Some unexpected implications of IP subsystems coupled with 3D IC assembly

Posted on July 19, 2012 by sleibson2

A new “Experts at the Table” conversation on the Semiconductor Manufacturing and Design Community (SMD) site about IP Subsystems among Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; … Continue reading →

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Beyond breakfast: An ethical bribe for attending “The Path to Yielding at 2(x)nm and Beyond” at DAC

Posted on May 15, 2012 by sleibson2

Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading →

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3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York

Posted on April 26, 2012 by sleibson2

Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading →

Posted in 20nm, 28nm, 3D, EDA360, Globalfoundries, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , , , | Leave a comment

You have six weeks to wait for the Semico IP Summit. What will you do until then?

Posted on March 30, 2012 by sleibson2

Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading →

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Common Platform: Why do these companies (IBM, Samsung, GLOBALFOUNDRIES) collaborate?

Posted on March 19, 2012 by sleibson2

Ana Hunter, Foundry Services VP at Samsung Semiconductor, had the honor of kicking off the Global Technology Forum in Silicon Valley. She decided to devote her short intro speech to answering the basic question about the Common Platform—a partnership among … Continue reading →

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By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley

Posted on March 5, 2012 by sleibson2

There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading →

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Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14

Posted on March 2, 2012 by sleibson2

The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum  rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading →

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3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

Posted on February 9, 2012 by sleibson2

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading →

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IBM to manufacture 32nm SOI chips with eDRAM in new GLOBALFOUNDRIES Fab 8 (Malta, NY)

Posted on January 10, 2012 by sleibson2

IBM is the first announced customer for GLOBALFOUNDRIES’ Fab 8 in Malta, NY. The companies plan to manufacture IBM’s 32nm SOI devices at the site using an SOI process technology. The new plant has already been facilitized with more than … Continue reading →

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Collaboration is key to making DFM work at 28nm and below

Posted on September 7, 2011 by sleibson2

At the final presentation I attended at last week’s Global Technology Forum, Manoj Chacko from Cadence discussed how to get “everything you’re entitled to” with In-Design DFM (Design for Manufacturing). Two of the key yield detractors Chacko discussed are yield … Continue reading →

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3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises

Posted on July 14, 2011 by sleibson2

Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading →

Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV | Tagged , , , , , , , , , , | 1 Comment

Globalfoundries, LSI Corp, and Broadcom help Editorial Director Ed Sperling give the industry a low-power report card. How did we score?

Posted on June 10, 2011 by sleibson2

On Wednesday at DAC’s show-floor Pavilion, Low-Power Engineering’s Editorial Director Ed Sperling chaired a panel with the intent of giving the industry a report card on its low-power engineering efforts. Along with Sperling on the Pavilion platform were Andrew Brotman, … Continue reading →

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Gartner’s Sam Wang tosses down the 28nm Silicon Realization gauntlet to IC design houses

Posted on May 19, 2011 by sleibson2

Sam Wang may have been a Gartner analyst for only six months or so, but he’s already learned how to drop a stunner on the audience. The event was today’s Gartner Semiconductor briefing at the San Jose Doubletree Hotel near … Continue reading →

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3D Thursday: Six more firms join Sematech 3D initiative

Posted on April 28, 2011 by sleibson2

EETimes’ Peter Clarke reports that six more companies have joined the Sematech 3D enablement program. The six new members are: Advanced Semiconductor Engineering Inc. (ASE) Altera Corp Analog Devices Inc. (ADI) LSI Corp On Semiconductor Corp Qualcomm Inc These six … Continue reading →

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Daniel Nenni’s 100th blog. (It’s about TSMC, no surprise)—Congratulations to Daniel

Posted on October 11, 2010 by sleibson2

Strategic Foundry Relationship expert and industry blogger Daniel Nenni has just published the hundredth entry in his Silicon Valley Blog. The topic is TSMC’s recent conference and Nenni, who writes a lot about TSMC, dishes up some cogent analysis and … Continue reading →

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ARM’s Cortex-A15: A big step up for the ARM processor architecture. Targeting 32nm and 28nm technology nodes.

Posted on September 28, 2010 by sleibson2

Earlier this week Cadence announced that it worked with ARM to develop an implementation methodology for the recently announced, high-end ARM Cortex-A15 processor core, code-named Eagle. The ARM Cortex-A15 processor core has an expanded 40-bit (1Tbyte) memory address space (called … Continue reading →

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