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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O Xilinx
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- The DDR4 SDRAM spec and SoC design. What do we know now?
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
- Need a scorecard for ARM processor core architectures?
- 3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron
- Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap
- Wolfson Microelectronics jams three 32-bit DSPs into an audio codec. Mixed-signal SoC and Silicon Realization walk in audio form
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
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Tag Archives: 2.5D
3D Thursday: Produce cost-effective 2.5D and 3D devices. Attend the Known Good Die conference, November 15
Robert Patti, Chief Technical Officer and VP of Design Engineering at Tezzaron Semiconductor is the just-announced speaker at the Known Good Die conference being held on November 15 in Santa Clara, CA. His topic: Using Repair & Redundancy with KGD … Continue reading
3D Thursday: Save the date. 3D Architectures for Semiconductor Integration and Packaging Conference on December 12-14
The 9th International 3-D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will be held December 12 -14, 2012 at the Sofitel in Redwood City, CA. It’s run by RTI International. More info here.
Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading
If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)
3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor
Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) … Continue reading
Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading
I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—‘Learn … Continue reading
Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading
Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die … Continue reading
Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric
The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading
3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.
The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading
What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading
3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That
If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading
Last Friday, I moderated an all-star, hand-picked 3D-IC panel at the Electronic Design Process Symposium (EDPS) in Monterey, California. The panel included: Phil Marcoux, Managing Director, PPM Associates, experienced packaging expert Herb Reiter, President of eda2asic, Chair of the Global … Continue reading
“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director … Continue reading
Last week’s Electronic Design Process Symposium (EDPS) opened a rich new vein of 3D IC material and you’ll see a lot nuggets from me on that topic in the next few days. Meanwhile, Richard Goering has already published a post … Continue reading
Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading
EDPS 3D Friday (April 6) expands with new speakers including 3D IC assembly and packaging advocate Phil Marcoux
I’ve written previously about the all-3D IC design, assembly, and packaging program that will take place during the second day of the EDPS (Electronic Design Process Symposium) workshop in Monterey. This blog post is to let you know that additional … Continue reading
This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of … Continue reading
3D Thursday: SEMATECH wades in to develop assessment criteria for 3D manufacturing equipment and processes
Earlier this week, SEMATECH—the global semiconductor industry’s research consortium—announced that it plans to conduct “Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high-volume manufacturing maturity issues” through its wholly owned … Continue reading
3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?
For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading
3D Week: The three interconnect crises of the electronics industry and the inevitability of 3D. Believable?
Many people in the electronics industry view 3D IC assembly as not being in the mainstream. That’s easy to understand. It’s not at the moment. Yet I do believe in the inevitability of 3D assembly. Here’s why. At last week’s … Continue reading
I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading
3D Thursday: Who is responsible for successful 2.5D and 3D assembly? eSilicon is perhaps saying “Us”
Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading