Tag Archives: Altera

3D Thursday: ARM, HP, and SK hynix join Hybrid Memory Cube Consortium (HMCC)

Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading

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Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can

Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading

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3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?

I just posted a blog entry about the Altera Optical FPGA that pumped 100Gigabit/sec Ethernet (GbE) traffic through a 3D-package-on-package-mounted, 12-channel optical interconnect device from Avago. (See “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle … Continue reading

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3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet

This week at the Optical Fibre Communication Conference and Exposition (OFC) in Los Angeles, Altera demonstrated a specially modified Stratix IV FPGA that handled bidirectional 100Gbps Ethernet (100GbE) traffic over a pair of IC-package-mounted Avago MicroPOD multi-lane optical transceivers. The … Continue reading

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading

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Who wants more technical detail on the Altera SoC FPGA? Altera says…you!

After the previous post on the announcement of the Altera SoC FPGA ran in EDA360 Insider—see “The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric”—I heard from people at Altera. They wanted … Continue reading

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3D Thursday: Hybrid Memory Cube—wide I/O only more so—gets an industry consortium

Back in August, I wrote about the 3D SDRAM assembly called the Micron Hybrid Memory Cube (HMC, see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) and I called it a … Continue reading

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The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric

It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product … Continue reading

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Friday video (late bonus): Altera demos some features from 28nm Stratix V FPGA

On Friday, Altera posted a video that shows the company characterizing some of the features of the upcoming Stratix V FPGA, being built with a 28nm process technology. The largest member of the Stratix V FPGA family will incorporate nearly … Continue reading

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Friday video (2fer): 28nm FPGA videos from Xilinx and Altera

Recently, Xilinx announced shipping early samples of its 28nm Kintex-7 FPGAs. Now 28nm is the current bleeding-edge process node for logic processes and it’s no small feat to start shipping parts—even early engineering samples—at this node. Here’s a video of … Continue reading

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