Category Archives: 2.5D

3D Thursday: Hella big conference on multi-die integration in the heart of Silicon Valley

There’s a strange little high-rise hotel called the Biltmore in the center of Silicon Valley at the intersection of the Montague Expressway and Highway 101. It’s going to be the site of this year’s “Roadmaps for Multi Die Integration” conference … Continue reading

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3D Thursday: Produce cost-effective 2.5D and 3D devices. Attend the Known Good Die conference, November 15

Robert Patti, Chief Technical Officer and VP of Design Engineering at Tezzaron Semiconductor is the just-announced speaker at the Known Good Die conference being held on November 15 in Santa Clara, CA. His topic: Using Repair & Redundancy with KGD … Continue reading

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3D Thursday: Save the date. 3D Architectures for Semiconductor Integration and Packaging Conference on December 12-14

The 9th International 3-D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will be held December 12 -14, 2012 at the Sofitel in Redwood City, CA. It’s run by RTI International. More info here.

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3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading

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3D Thursday: Will water cooling for 3D IC assemblies ever be practical?

Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading

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3D Thursday: Magnificent Max explains 3D IC in simple terms

If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)

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3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor

Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) … Continue reading

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3D Thursday: What the Cadence purchase of signal- and power-integrity EDA toolmaker Sigrity means for 2.5D and 3D IC assembly

Richard Goering has just published an in-depth analysis in his Industry Insights blog that explains what the Cadence purchase of signal- and power-integrity EDA toolmaker Sigrity means for pcb and IC package designers. Goering quotes Brad Griffin, product marketing director … Continue reading

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Innovate or die! A high-tech parable from this week’s Time Magazine

Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading

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Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can

Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading

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Friday Video: Mr. 3D IC, Herb Reiter, speaks about his start with 3D, where it is, where it’s going

I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—‘Learn … Continue reading

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3D Thursday: SemiWiki’s Paul McLellan on the TSMC/Cadence 3D collaboration

Briefly noted: SemiWiki’s Paul McLellan has just published a short analysis of the 3D announcements made last week at DAC by TSMC and Cadence.

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3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

3D Thursday: Want to see a closeup of the TSMC 3D IC test vehicle?

Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die … Continue reading

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Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric

The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading

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3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.

The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading

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3D Thursday: 3D IC success stories—a DAC panel. June 7

What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading

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3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That

If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading

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3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading

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3D Thursday: The low down on low-power CPU-memory connections from EDPS

Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques. Not simply because Wide I/O … Continue reading

Posted in 2.5D, 3D, EDA360, Memory, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , | Leave a comment

3D Thursday: A funny thing happened to me on the EDPS 3D-IC panel

Last Friday, I moderated an all-star, hand-picked 3D-IC panel at the Electronic Design Process Symposium (EDPS) in Monterey, California. The panel included: Phil Marcoux, Managing Director, PPM Associates, experienced packaging expert Herb Reiter, President of eda2asic, Chair of the Global … Continue reading

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Want a peek at a possible Qualcomm 3D IC roadmap?

“3D IC test wafers will run this year and high-volume 3D IC manufacturing will start in 2013,” concluded Riko Radojcic at the end of his EDPS keynote on 3D ICs held in Monterey, California last Friday. Radojcic is Qualcomm’s Director … Continue reading

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3D preview from EDPS: Qualcomm’s Director of Engineering Riko Radojcic talks 3D and 3D EDA

Last week’s Electronic Design Process Symposium (EDPS) opened a rich new vein of 3D IC material and you’ll see a lot nuggets from me on that topic in the next few days. Meanwhile, Richard Goering has already published a post … Continue reading

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3D Thursday: A quick look at glass interposers for 3D IC assembly

3D InCites just published a short piece on glass interposers for 3D ICs, as discussed at the 2012 IMAPS International Device Packaging conference, held March 5-8 in Scottsdale, AZ. If you’re interested in seeing a more technical presentation on the … Continue reading

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3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!

Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading

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