Category Archives: Packaging

3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power

Posted on August 29, 2012 by sleibson2

Wednesday at the Hot Chips 24 conference, Rumi Zahir of Intel discussed the company’s Penwell SoC designed for cell phone handsets. The SoC is employed in the Medfield cellular handset design and it’s based on the Intel Atom x86 processor … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | 7 Comments

3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Posted on June 13, 2012 by sleibson2

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading →

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

Moore’s Law: Wanted, Dead or Alive

Posted on May 14, 2012 by sleibson2

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading →

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.

Posted on May 9, 2012 by sleibson2

The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading →

Posted in 2.5D, 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , | Leave a comment

3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That

Posted on May 2, 2012 by sleibson2

If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading →

Posted in 2.5D, 3D, Packaging, Silicon Realization, TSMC | Tagged , , , , , | Leave a comment

3D Thursday: The low down on low-power CPU-memory connections from EDPS

Posted on April 18, 2012 by sleibson2

Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques. Not simply because Wide I/O … Continue reading →

Posted in 2.5D, 3D, EDA360, Memory, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , | Leave a comment

3D Thursday: A quick look at glass interposers for 3D IC assembly

Posted on March 22, 2012 by sleibson2

3D InCites just published a short piece on glass interposers for 3D ICs, as discussed at the 2012 IMAPS International Device Packaging conference, held March 5-8 in Scottsdale, AZ. If you’re interested in seeing a more technical presentation on the … Continue reading →

Posted in 2.5D, 3D, EDA360, Packaging, Silicon Realization | Tagged , | Leave a comment

3D Thursday: TSMC talks more about Moore, More than Moore, and 3D ICs at CDNLive!

Posted on March 15, 2012 by sleibson2

Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading →

Posted in 10nm, 14nm, 2.5D, 3D, CDNLive!, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet

Posted on March 7, 2012 by sleibson2

This week at the Optical Fibre Communication Conference and Exposition (OFC) in Los Angeles, Altera demonstrated a specially modified Stratix IV FPGA that handled bidirectional 100Gbps Ethernet (100GbE) traffic over a pair of IC-package-mounted Avago MicroPOD multi-lane optical transceivers. The … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

ARM big.LITTLE multicore IP architecture wins a Microprocessor Report Analysts’ Choice Award

Posted on January 24, 2012 by sleibson2

This week in the Microprocessor Report, the Linley Group announced its Analysts’ Choice Award winners and declared the ARM big.LITTLE multicore IP architecture as the best processor IP of the year: “Designed to extend battery life by up to 70%, … Continue reading →

Posted in ARM, Cortex-A15, Cortex-A7, EDA360, IP, Low Power, Packaging, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

3D Thursday: Cypress subsidiary Deca Technologies is onto making silicon interposers for 2.5D packaging in a big way. What if 2.5D got really cheap?

Posted on November 17, 2011 by sleibson2

Last week, Deca Technologies unstealthed. I found out through an article in the San Jose Mercury News. Deca is an independent subsidiary of Cypress Semiconductor. I zipped to the Deca Web site (once I located it), and found this quote … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization | Tagged , , | 1 Comment

Who else wants to learn high-speed PCB design and signal integrity analysis from world-renown expert Robert Hanson—for FREE?

Posted on November 10, 2011 by sleibson2

Do the words “high-speed PCB design” make you twitch uncontrollably? How about “signal integrity analysis”? “Crosstalk”? Perhaps the phrase “complex power-delivery networks” is your nemesis. All of these topics can be real bears to deal with when you are laying … Continue reading →

Posted in EDA360, Packaging, pcb | Tagged , , , , , | 1 Comment

3D Thursday: AMD Radeon E6460 embedded graphics processor employs two kinds of 3D assembly. One may really surprise you

Posted on September 29, 2011 by sleibson2

Earlier this week, AMD launched the Radeon E6460 embedded GPU  (graphics processor, see photo below). It’s an entry-level GPU with more than 2x the performance of the previous-generation Radeon E2400 GPU. To get the desired performance from this GPU—it’s capable … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization | Tagged , , , | 2 Comments

3D Thursday: Design 3D die stacks with test in mind

Posted on September 15, 2011 by sleibson2

You can read an excellent new article on test challenges for 3D IC design here. The article was written by Samta Bansal of Cadence and Herb Reiter, Chair of the GSA’s 3D-IC working Group. The article discusses the key differences … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC Realization, System Realization | Leave a comment

3D Thursday: Feedback on last week’s blog post about 3M/IBM agreement to work on heat-conductive 3D assembly adhesives

Posted on September 15, 2011 by sleibson2

Last Thursday, I wrote a blog entry on the agreement between IBM and 3M to develop advanced adhesives to aid in 3D die-stack assembly and heat removal. (See “3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway … Continue reading →

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3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway to heaven with glue?

Posted on September 8, 2011 by sleibson2

IBM and 3M have announced a program to develop heat-dissipating adhesives that would permit the construction of tall, 3D “towers” of silicon chips in 3D assemblies. The stated target: 100 stacked chips. Some things about 3D assembly are absolutely uncontroversial: … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC Realization | Tagged , , | 1 Comment

3D Thursday: Raspberry Pi Foundation’s $25 ARM board boots Linux using stacked DRAM

Posted on August 25, 2011 by sleibson2

Although it’s not presented at a 3D story to the public, the Raspberry Pi Foundation’s $25 alpha board based on a 700MHz ARM 11 processor is very much 3D because there’s an SDRAM stacked on top of the processor. Why? … Continue reading →

Posted in 3D, EDA360, Firmware, Linux, Memory, Packaging, Silicon Realization | Tagged , | Leave a comment

Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?

Posted on August 22, 2011 by sleibson2

Last week, I quoted Ann Steffora Mutschler’s article about the information that Micron has revealed about it’s 3D Hybrid Memory Cube. Now that I’ve got the paper Micron presented at last week’s Hot Chips 23 conference, I’d like to explain … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, TSV | Tagged , , , , | 2 Comments

Friday Video: What’s Next For Memory Designs In 2012? – from Agilent

Posted on August 5, 2011 by sleibson2

Agilent has created a 6-part video series titled “What’s Next For Memory Designs In 2012?” that’s well worth a look. There’s about 30 minutes of video total, chopped into 2-8 minute pieces that you’ll want to watch if you have any … Continue reading →

Posted in EDA360, Memory, Packaging, System Realization | Tagged , , , , | 1 Comment

DFT for 3D-IC: It’s déjà vu all over again

Posted on August 2, 2011 by sleibson2

Reading Richard Goering’s blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass up a chance to quote the great … Continue reading →

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Friday Video: Teardown of iRiver Story HD eBook by EEVBlog’s Dave Jones

Posted on July 29, 2011 by sleibson2

Dave Jones down in Australia loves to tear electronic products apart on video and while he’s certainly entertaining, he’s also very educational from a System Realization perspective. I never fail to learn at least one new thing from his unique … Continue reading →

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3D Thursday: Power is a killer app for TI’s PowerStack 3D packaging—parasitics vanish

Posted on July 28, 2011 by sleibson2

Most discussions of 3D packaging involve silicon chips with millions and millions of transistors. Billions in the case of memory chips. TI’s PowerStack 3D packaging skews all the way to the other end of the spectrum. The die packaged in … Continue reading →

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3D Thursday: GSA working on 3D IC report covering benefits of and barriers to adoption

Posted on April 28, 2011 by sleibson2

Just got an email from the GSA (www.gsaglobal.org) that it is working on a report titled “3D IC Architecture: A Natural Evolution” to be published in the second half of the year. Currently, the document is merely an abstract that … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, System Realization | Tagged , | 1 Comment

What’s driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?

Posted on April 12, 2011 by sleibson2

The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul … Continue reading →

Posted in 3D, Design Abstraction, Design Convergence, Design Intent, EDA360, Low Power, Packaging, Silicon Realization, SoC Realization, System Realization, Verification | Leave a comment

Herb Reiter on the 3D landscape as he sees it today

Posted on April 11, 2011 by sleibson2

Herb Reiter is the industry’s cheerleader for 3D assembly. He’s the president of his own company, EDA2 ASIC, and he’s a 3D consultant to the Global Semiconductor Alliance. Reiter has been trying to pull the industry into 3D mode for … Continue reading →

Posted in 3D, Packaging, System Realization | Leave a comment