Category Archives: SoC Realization

Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.

Rick Merritt has just published an interesting article in EETimes: the PCI Special Interest Group (PCI SIG) expects to announce an adaptation of the ever-popular PCIe interface for mobile devices including smartphones. Merritt reports that the PCI SIG and MIPI … Continue reading

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Posted in EDA360, IP, Mobile, SoC Realization, System Realization | Tagged , , , | 2 Comments

3D Thursday: Hella big conference on multi-die integration in the heart of Silicon Valley

There’s a strange little high-rise hotel called the Biltmore in the center of Silicon Valley at the intersection of the Montague Expressway and Highway 101. It’s going to be the site of this year’s “Roadmaps for Multi Die Integration” conference … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization | Leave a comment

TI Stellaris LaunchPad eval board features ARM Cortex-M4F. Intro price: $4.99. Get yours now.

  Texas Instruments’ Stellaris LM4F120H5QRC microcontroller is based on an 80MHz copy of the ARM Cortex-M4F processor core with an integrated single-precision floating-point unit. It also includes 256Kbytes of Flash memory, 32Kbytes of SRAM, 2Kbytes of EEPROM, and a host … Continue reading

Posted in ARM, Cortex-M4, EDA360, SoC Realization, Texas instruments | Tagged , , , , | Leave a comment

3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power

Wednesday at the Hot Chips 24 conference, Rumi Zahir of Intel discussed the company’s Penwell SoC designed for cell phone handsets. The SoC is employed in the Medfield cellular handset design and it’s based on the Intel Atom x86 processor … Continue reading

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | 7 Comments

Zowie! More than 50 x86 cores on the Intel Knights Corner Manycore Coprocessor

Today at the Hot Chips 24 conference, George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip, to be formally called the Intel Xeon Phi coprocessor. This chip runs Linux, but it’s designed to act … Continue reading

Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , | 2 Comments

Daniel Nenni at SemiWiki publishes a [very] brief history of the SoC

Daniel Nenni has just posted a very brief history of the SoC, with heavy emphasis on SoCs for mobile products. The emphasis is probably warranted because mobile designs really have driven SoC design for the past decade. One of the … Continue reading

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Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading

Posted in Memory, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | Leave a comment

Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges

A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across … Continue reading

Posted in EDA360, Mixed Signal, Silicon Realization, SoC, SoC Realization, Verification | Tagged , , , , | Leave a comment

Samsung Exynos 5 Dual mobile processor features two 1.7GHz ARM Cortex-A15 processors, a WQXGA display controller, and two LPDDR3 controllers to feed ‘em

This past weekend, the Web was abuzz with last week’s unveiling of Samsung’s Exynos 5 Dual mobile processor. This SoC features two 1.7GHz ARM Cortex-A15 processors rather than the previous Exynos generation Dual mobile processor that incorporated two 1.4GHz ARM … Continue reading

Posted in Cortex-A15, EDA360, Samsung, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

Looking for an introductory Verilog book? How’s $24.95 sound?

Bob Zeidman, founder and president of Zeidman Consulting, has just published the third edition of his book “Introduction to Verilog.” It was first published a dozen years ago and is based on the Verilog seminars that Zeidman has given at … Continue reading

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Need to make an ARM Cortex-A9 processor core all it can be?

A new blog published today on the ARM Web site titled “How do you take an ARM POP up one more notch?” describes a very recent collaboration between ARM and Cadence to enhance the ARM POP IP, which helps any … Continue reading

Posted in 40nm, ARM, Cortex-A9, Silicon Realization, SoC, SoC Realization, TSMC | Tagged , , , , | Leave a comment

If Aladdin’s Genie lived in a Computer-on-Module, it might look like the Gumstix Overo

One of the funniest lines in the 1992 animated Disney movie “Aladdin” is when the frenetic blue Genie, voiced by the incredible Robin Williams, describes his situation: “PHENOMENAL COSMIC POWERS; Itty-bitty living space,” referring to his life in a lamp. … Continue reading

Posted in ARM, Cortex-A8, SoC, SoC Realization, System Realization, Texas instruments | Tagged , , , , , , | Leave a comment

5-minute, 20nm Q&A. All you need to know in 5 minutes.

What are the key advantages of moving to 20nm? There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA). Essentially, this is a “next-node” answer, which is still as … Continue reading

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Cavium “Thunders” approval of 64-bit ARM v8 processor cores for cloud and server apps

In an unusual press release, network processor vendor Cavium has revealed plans for Project Thunder,” which will develop a family of multi-core SoCs based on the 64-bit ARM v8 processor architecture. The processors will be full-custom cores based on the … Continue reading

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3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O | Tagged , , , , , | Leave a comment

3D Thursday: Will water cooling for 3D IC assemblies ever be practical?

Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , | Leave a comment

3D Thursday: Magnificent Max explains 3D IC in simple terms

If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , | Leave a comment

Can 1000 processors dance on the head of a pin? MIT’s Professor Srini Devadas hopes so

Veteran EDA industry watcher Peggy Aycinena visited MIT recently and spoke with Professor Srini Devadas about a manycore processor project called “Angstrom.” The purpose of the project is to develop massively parallel hardware—as in 1024 processors—to explore better ways of … Continue reading

Posted in Apps, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | Leave a comment

Two more low-cost dev boards based on the ARM Cortex-M4 with 1Mbyte of Flash, 192Kbytes of RAM: $15.57 and up

Thanks to http://www.chibios.org, I’ve just learned of two low-cost development boards based on the STMicroelectronics STM32F07 microcontroller. You might be interested in these boards because one costs $15.57 and the other sells for 39.95€. The lower-cost board is from STMicroelectronics … Continue reading

Posted in ARM, Cortex-M4, SoC, SoC Realization | Tagged , , , , , , , , , , | Leave a comment

ARM, TSMC announce collaboration on FINfet-based ARM v8 processor core for sub-20nm SoC designs

Today, ARM and TSMC announced a multi-year deal to develop a 64-bit ARM v8 processor “beyond” the 20nm node using FINfets. The collaboration includes the ARMv8 architecture, ARM Artisan physical IP, and TSMC’s FinFET process technology. The target of this … Continue reading

Posted in 10nm, 14nm, 20nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , | Leave a comment

Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence

On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading

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3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor

Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , | Leave a comment

Innovate or die! A high-tech parable from this week’s Time Magazine

Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading

Posted in 2.5D, 20nm, 28nm, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , | Leave a comment

High-level synthesis, C versus assembly code, and Leibson’s Law

Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading

Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC | Tagged , , , , | Leave a comment

Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.

You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading

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