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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Category Archives: Mixed Signal
Daniel Payne reviews new Mixed-Signal Methodology book. He enjoyed it. Discount ends tomorrow!
SemiWiki blogger and EDA Consultant Daniel Payne has just published a second, more extensive review of the new Mixed-Signal Methodology book just published by Cadence. He has included extensive technical information from the book in his review, so if you’re … Continue reading
Posted in EDA360, Mixed Signal
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Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley
A 1-day workshop on Analog and Mixed-Signal Design Automation will be held on November 8 in conjunction with ICCAD in Silicon Valley. It’s no secret that advanced-node process scaling makes all IC design more complex and more challenging—even more so … Continue reading
Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across … Continue reading
Posted in EDA360, Mixed Signal, Silicon Realization, SoC, SoC Realization, Verification
Tagged Boeing, Cadence, Mixed Signal, Qualcomm, SoC
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New Mixed-Signal Methodology Guide provides design, verification and implementation methodologies for advanced mixed-signal designs
Cadence has just published the “Mixed-Signal Methodology Guide,” which provides an overview of design, verification and implementation methodologies for advanced mixed-signal designs based on recommendations from the book’s co-authors—top mixed-signal design experts from across the industry including authors from Boeing, … Continue reading
Friday Video: Freescale pits Kinetis L microcontroller against parts from Microchip, TI, and Renesas. Guess who wins the low-power derby?
I’ve written a lot this week about the low-power Kinetis L microcontroller from Freescale, a low-power, mixed-signal IC design now shipping in alpha silicon. I have just found this new Freescale video, which was probably shot at this week’s Freescale … Continue reading
Posted in ARM, Cortex-M0, EDA360, Low Power, Mixed Signal, Silicon Realization, SoC, SoC Realization
Tagged ARM architecture, Cortex-M0, Freescale, Freescale Semiconductor, microcontroller
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The Freescale Kinetis L microcontrollers based on the ARM Cortex-M0+ processor core: But what do they do???
A couple of days ago, I wrote that Freescale had announced that it was shipping alpha samples of its new Kinetis L microcontroller, which is based on the 32-bit ARM Cortex-M0+ processor core. (See “Freescale starts sampling $0.49 Kinetis L … Continue reading
Posted in Cortex-M0, EDA360, Mixed Signal, SoC, SoC Realization
Tagged ARM architecture, Cortex-M0, Flash memory, Freescale, Freescale Kinetis L, Freescale Semiconductor
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What effect does the ARM Cortex-M0 core have on mixed-signal microcontroller design?
Earlier this month at DAC, ARM, NXP, and Cadence hosted a panel on mixed-signal design as it applies to microcontroller design. Richard Goering posted a great summary of the topics discussed at the panel, but I want to tease out … Continue reading
Posted in ARM, Cortex-M0, EDA360, Low Power, Mixed Signal, SoC, SoC Realization, System Realization
Tagged 32-bit, ARM, ARM architecture, Flash, microcontroller, NXP Semiconductors
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Meaty new book on Mixed-Signal SoC Design, Verification and Implementation Methodology is nearly ready
Is your current SoC project a mixed-signal design? If not, chances are good that the next one will be. That’s because there’s been an evolution in SoC design from pure digital to analog/mixed-signal (AMS) designs over the past several years … Continue reading
Freescale starts sampling $0.49 Kinetis L microcontrollers based on ARM Cortex-M0+ processor core
There are two major reasons for reading this blog post: A 32-bit microcontroller that sells for as little as $0.49 in 10K quantities and consumes 50µA/MHz A $12.95 development board to be available late in September These are two of … Continue reading
DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping
Tagged DAC, EDA, IC design, pcb, synthesis, verification
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Smart analog/mixed-signal IC designs are—er—smarter. Learn how to stuff a 32-bit ARM Cortex-M core into an AMS design at DAC. Lunch included
In these days of the SoC, one chip has to do it all. That means both analog and digital processing. Now you can get a first-hand look at how successful design teams have integrated ARM Cortex-M processor cores in their … Continue reading
Posted in ARM, Cortex-M0, Cortex-M4, DAC, Mixed Signal, Silicon Realization, SoC, SoC Realization
Tagged AMS, ARM architecture, ARM Cortex-M, Moscone Center, San Francisco, System-on-a-chip
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FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST
Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading
Posted in Analog, EDA360, Mixed Signal, Silicon Realization, Verification
Tagged AMS, Analog, Mixed Signal, SV-AMS, SystemVerilog, verification
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