3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!

Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so comprehensive that I simply cannot summarize it in one blog entry, so I plan to chip it up into relevant pieces and will discuss the topics over several blog entries. Frankly, I cannot believe that Xilinx is giving this much hard-won information away, for free no less, so I strongly recommend that you go a get a copy of this White Paper before Xilinx CEO Moshe Gavrielov comes to his senses.

Today’s 3D Thursday so I will focus on the White Paper’s discussion of the low-power aspects of the Xilinx Stacked Silicon Interconnect (SSI) technology, which employs 2.5D packaging using a silicon interposer. (See the two previous EDA360 Insider blog posts: “Need really big FPGAs? Xilinx will be taking the ‘3D’ route for initial Virtex 7 parts” and “3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?”) Now the packaging and cost benefits of this 2.5D packaging approach are pretty clear. Xilinx uses SSI technology so that it can build larger FPGAs than it can economically manufacture if it were to take a strictly monolithic approach. Defect densities and all that. But there are also at least two major low-power aspects to this 2.5D packaging. Both are easily understood.

To understand the first major low-power aspect of the Xilinx SSI packaging technology, a bit of review is in order. Here’s what I wrote in a previous blog entry:

“The device uses a passive silicon interposer manufactured with 65nm design rules—with through-silicon vias (TSVs) but no active devices on the silicon—as a circuit board for the 28nm silicon FPGA slices or tiles. The silicon interposer provides high-density interconnect between the FPGA slices and also serves as a dimensional translator between the 28nm FPGA slices with their fine-pitched microbumps and the package substrate with conventional C4 solder bumps.”

“’Because we are using chip interconnect to connect the dice, it is much more economical in power than connecting dice through big traces, through packages or through circuit boards,’ says Liam Madden, the Xilinx corporate VP of FPGA development and silicon technology.”

According to the new Xilinx White Paper, using transceivers designed for on-chip interconnect to drive fine-pitch traces on the silicon interposer reduces I/O power consumption by two orders of magnitude compared to building the equivalent interconnectivity with normal chip-to-board or chip-to-chip I/O transceivers. That’s a big number worth paying attention to if you’re facing a design that has a lot of off-die interconnect. Think of the power you might save if you knew you were going to use 2.5D packaging to bundle logic with memory, for example. Now the 3D advocates will say “nothing new here” because they’ve been talking about this particular advantage for years. Yet this Xilinx White Paper makes this advantage more than theoretical. It makes it real (at least it does for me).

The second big advantage made possible by 2.5D packaging arises from the identical function of the FPGA slices Xilinx uses to build these 2.5D Series 7 FPGAs. For this, I’m going to quote directly from the Xilinx White Paper because it’s said so clearly, I need not gloss the prose:

“Worst case leakage can become a serious problem as the FPGAs get larger because each transistor has a leakage component and some of the larger devices can be upwards of one billion transistors. The larger 7 series FPGAs, such as the XC7V1500T and XC7V2000T, are created using Xilinx’s stacked silicon interconnect technology. Simply stated, this technology uses multiple dies to create a single large device. One benefit of the stacked silicon interconnect technology is the reduction in maximum static power compared to a similar sized device with a standard monolithic die.

For example, if one die represents 500K logic cells with X units of typical leakage and 2X units of worst case leakage, a 1,500K logic cell device without stacked silicon interconnect technology has worst case leakage of approximately 6X units. But with stacked silicon interconnect technology and Xilinx’s low-power strategy; a 1,500K logic cell device could have worst case leakage of only 3.6X units, a 40% reduction in worst case leakage power.

Xilinx actively decided to never place all worst case leakage dies in a single device. One die might be close to the worst case leakage but the other dies in the device will be closer to typical. The result is a much lower worst case leakage specification compared to a single die with the same density.”

Got it? The FPGA slices are all functionally identical, but they may not all have the same leakage characteristics because of process variation. So 2.5D packaging gives Xilinx the ability to mix and match otherwise identical die with different power-consumption characteristics to meet an overall power-consumption objective for the packaged part. You may not have FPGA slices available but if you’re using 3D packaging, you probably will be using multiple memory die. The same advantage applies to memory as it does to FPGA slices.

So far, I’ve covered about one page of this Xilinx White Paper out of 25 pages. It is truly meaty, beaty, big, and bouncy. Like I wrote above in the introduction to this blog entry, go get a copy of this White Paper before it’s no longer available. You never know, this kind of hard-earned knowledge might just come in handy.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization, SoC Realization and tagged , , , . Bookmark the permalink.

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