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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: IP
Gary Smith’s Sunday Pre-DAC talk to focus on Multi-platform-based SoC Design Methodology
For years, EDA Analyst Gary Smith has given a pre-DAC talk on the major trends in EDA and in the design of SoCs and ICs. This year is no exception. Smith has reserved Salon 6 at the San Francisco Marriott … Continue reading
Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics
Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading
Posted in 3D, Apps, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, EDA, IP, IP Integration, Lego, Low Power, Mentor Graphics, Synopsys
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The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman
Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting: “In my mind an IP subsystem is a set … Continue reading
Posted in EDA360, IP, SoC, SoC Realization, System Realization
Tagged ASIC, ChipEstimate, IP, SoC, Subsystems
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Semico to hold IP Ecosystem conference in Silicon Valley on May 16
Chips no longer get designed without a substantial amount of commercial IP (both design IP and verification IP) and the business is now plenty big enough to merit its own conference. So research firm Semico is holding the IMPACT conference … Continue reading
Who else wants to see a 60x speedup in DFM signoff on a 28nm design?
Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES’ DRC+ methodology. This approach to DRC is interesting because it’s the industry’s first approach to DRC that teams … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 28nm, 32nm, Design rule checking, DRC, IP, Rambus
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Amazon’s cloud service crash permanently lost data. Think this has implications for EDA?
Today, MSNBC’s Technolog carries an article by Henry Blodget that discusses another aftermath of the Amazon EC2 (Elastic Compute Cloud) services failure: lost data. The article quotes a letter from Amazon stating: “A few days ago we sent you an … Continue reading
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