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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: SystemC
High-level synthesis, C versus assembly code, and Leibson’s Law
Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading
Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC
Tagged ASIC, High-level synthesis, LinkedIn, SoC, SystemC
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Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development
In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging … Continue reading
System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
IEEE Computer Society Lecture—Creating System-On-Chips: Mixing HW & SW Successfully
As soon as we started to incorporate processors on ASICs, thus instantly creating SoCs, hardware/software integration issues became fully intertwined with chip design. Today, we routinely put a dozen or more firmware-driven processing elements on our SoCs so the issues … Continue reading
Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading
Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM
Tagged Accellera, EDA, IEEE 1666, OSCI, SoC Realization, SystemC, TLM
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Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible
As of today, you can start to develop application software for the Xilinx Zynq-7000 family of Extensible Processing Platforms (EPP) using a virtual prototyping platform announced today and jointly developed by Xilinx and Cadence. The virtual platform provides an accurate … Continue reading
Posted in Apps, ARM, Cortex-A9, EDA360, FPGA prototyping, SoC Realization, System Realization, TLM, Virtual Prototyping
Tagged ARM Cortex-A9, Cadence, Linux, Multi-core processor, SystemC, Xilinx
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Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading
Posted in System Realization, SystemC, UVM, Verification
Tagged Accelera, SystemC, SystemVerilog, TLM, UVM
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OSCI and Accelera merger: And now the rest of the story courtesy of Stan Krolikoski
Accelera and OSCI (the SystemC standardization guys) announced their intent to merge this last week. Interoperability standards at multiple levels are important, so this is indeed an important announcement. Stan Krolikoski, Group Director for EDA/IP Standards & Interoperability at Cadence, … Continue reading
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