Tag Archives: Low Power

Low-Power Design: Is the Problem Solved?

“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading

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Power is everything in design today. Believe it?

Brian Bailey has just published an article on low-power design in the EE Life section of EETimes. (See “Power 101 – Power consumption”) Here is Bailey’s premise: “Power, in my opinion, has become a game changer, not just for hardware … Continue reading

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There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?

There are a range of low-power design approaches for ASIC design including: Clock Gating Multi-Voltage Power Shutoff Dynamic Voltage Body Bias Adaptive Voltage All of the above Used in combination, there are more than 80,000 possible low-power modes that all … Continue reading

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Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics

Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading

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DARPA wants a more PERFECT processing engine with a 75x improvement in GFLOPS/Watt. Want to play?

Further proof that power consumption now rules the design envelope is the announcement of DARPA-BAA-12-24 calling for an increase in embedded computing power efficiency from approximately 1 GFLOPS/W to 75 GFLOPS/W. If you think all of that efficiency improvement is … Continue reading

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Free Webinar on December 8: Mixed-signal and low-power analysis and verification techniques

As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range … Continue reading

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6-Part series of blog posts on 28nm low-power design

Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading

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Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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Friday video: How low is low power? Energy Micro video puts “sleep mode” into question

Time was, there was at most one sleep mode for a microcontroller and the only thing the micro did in that mode was pay attention to an interrupt. Energy Micro has extended its Gecko series of ARM-based microcontrollers with a … Continue reading

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