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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: Low Power
Low-Power Design: Is the Problem Solved?
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Posted in EDA360, IP, Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged CPF, Low Power, PSOC, RTL, SoC
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Power is everything in design today. Believe it?
Brian Bailey has just published an article on low-power design in the EE Life section of EETimes. (See “Power 101 – Power consumption”) Here is Bailey’s premise: “Power, in my opinion, has become a game changer, not just for hardware … Continue reading
Posted in Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged Brian Bailey, EE Times, Jan Rabaey, Low Power
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There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?
There are a range of low-power design approaches for ASIC design including: Clock Gating Multi-Voltage Power Shutoff Dynamic Voltage Body Bias Adaptive Voltage All of the above Used in combination, there are more than 80,000 possible low-power modes that all … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization
Tagged ASIC, Low Power, verification
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Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics
Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading
Posted in 3D, Apps, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, EDA, IP, IP Integration, Lego, Low Power, Mentor Graphics, Synopsys
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Free Webinar on December 8: Mixed-signal and low-power analysis and verification techniques
As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range … Continue reading
Posted in AMS, EDA360, Silicon Realization, SoC, Verification
Tagged Analog, ASIC, Low Power, Mixed Signal
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6-Part series of blog posts on 28nm low-power design
Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization
Tagged 28nm, FPGA, Low Power, process technology, Xilinx
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Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
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Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
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Friday video: How low is low power? Energy Micro video puts “sleep mode” into question
Time was, there was at most one sleep mode for a microcontroller and the only thing the micro did in that mode was pay attention to an interrupt. Energy Micro has extended its Gecko series of ARM-based microcontrollers with a … Continue reading
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