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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- ARM unveils 64-bit v8 architecture at ARM TechCon 2011
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Tag Archives: SoC
3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
Wednesday at the Hot Chips 24 conference, Rumi Zahir of Intel discussed the company’s Penwell SoC designed for cell phone handsets. The SoC is employed in the Medfield cellular handset design and it’s based on the Intel Atom x86 processor … Continue reading
Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization
Tagged eMMC, Intel, Intel Atom, LPDDR2, Medfield, mobile phone, SDRAM, SoC
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Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across … Continue reading
Posted in EDA360, Mixed Signal, Silicon Realization, SoC, SoC Realization, Verification
Tagged Boeing, Cadence, Mixed Signal, Qualcomm, SoC
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High-level synthesis, C versus assembly code, and Leibson’s Law
Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading
Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC
Tagged ASIC, High-level synthesis, LinkedIn, SoC, SystemC
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Meaty new book on Mixed-Signal SoC Design, Verification and Implementation Methodology is nearly ready
Is your current SoC project a mixed-signal design? If not, chances are good that the next one will be. That’s because there’s been an evolution in SoC design from pure digital to analog/mixed-signal (AMS) designs over the past several years … Continue reading
Gary Smith’s Sunday Pre-DAC talk to focus on Multi-platform-based SoC Design Methodology
For years, EDA Analyst Gary Smith has given a pre-DAC talk on the major trends in EDA and in the design of SoCs and ICs. This year is no exception. Smith has reserved Salon 6 at the San Francisco Marriott … Continue reading
Networks on Chip: Redux, Redux, Redux
There must be some way out of here Said the joker to the thief There’s too much confusion I can’t get no relief – “All Along the Watchtower,” Bob Dylan During the late 1980s and early 1990s, we had around … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged Babel, Bob Dylan, Ethernet, Massachusetts Institute of Technology, MIT, Network On Chip, NoC, SoC
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Jim Hogan’s top six SoC trends for 2012. Want to know what they are?
Jim Hogan was the EDPS dinner speaker last week at the Monterey Peninsula Yacht Club and he held the audience captive for quite a while. Hogan is a well-known EDA venture capitalist. One of the highlights of his talk was … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged Jim Hogan, PPA, SoC
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Low-Power Design: Is the Problem Solved?
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Posted in EDA360, IP, Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged CPF, Low Power, PSOC, RTL, SoC
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You have six weeks to wait for the Semico IP Summit. What will you do until then?
Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading
Posted in EDA360, IP, SoC Realization
Tagged Advanced Micro Devices, Cadence, GlobalFoundries, Mentor Graphics, SoC, Synopsys, TSMC
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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman
Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting: “In my mind an IP subsystem is a set … Continue reading
Posted in EDA360, IP, SoC, SoC Realization, System Realization
Tagged ASIC, ChipEstimate, IP, SoC, Subsystems
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Semico to hold IP Ecosystem conference in Silicon Valley on May 16
Chips no longer get designed without a substantial amount of commercial IP (both design IP and verification IP) and the business is now plenty big enough to merit its own conference. So research firm Semico is holding the IMPACT conference … Continue reading
Do you know all of the essential aspects of VIP to make a good make/buy decision?
The growth of standards-based interfaces and the rapid advance in the state of the art for SoC design have created a real need for pro-quality verification IP (VIP). One interesting facet of VIP development is its parallel evolution with design … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Verification, VIP
Tagged SoC, verification, VIP
2 Comments
Power-intent methodologies: Can’t we all just get along?
All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization
Tagged ASIC, CPF, IEEE 1801, Silicon Realization, SoC, System-on-a-chip, UPF
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3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics
Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged JEDEC, mobile phone, Renesas, SoC, Wide I/O
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The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
I’ve written up many bits of wisdom from my friend Jack Ganssle before and his latest Embedded Muse newsletter carries a lead article on the new ARM big.LITTLE design philosophy that teams a high-powered ARM Cortex-A15 processor core with a … Continue reading
Posted in Android, ARM, Cortex-A15, Cortex-A7, SoC, SoC Realization, System Realization
Tagged ARM, ARM Cortex-A15, ARM Cortex-A7, Cortex-A15, Cortex-A7, Ganssle, SoC
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Friday Video (late): Want more info on the AppliedMicro 64-bit ARM v8 X-Gene server SoC? Photos and a link to a video
AppliedMicro rolled out its 64-bit, ARM v8-based X-Gene server SoC last week at ARM TechCon 2011. The company put on a 1-hour presentation that I unfortunately missed. However, the presentation with slides is now on line and they will provide … Continue reading
Posted in ARM, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 64-bit, AppliedMicro, ARM v8, server, SoC, X-Gene
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Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips
EDA360 Insider followers will not be surprised to hear that Semico’s latest blog entry on Semico Spin claims that “Special Purpose Logic”—consisting of ASICS, ASSPs, SoCs, and core-based ICs—is now the fastest growing category for MOS logic chips and has … Continue reading
Check your system-level design assumptions at the door
Jon McDonald’s opinion piece, just published in the System-Level Design Community section of Chip Design Magazine’s site, is about assumptions built into the design of complex electronic systems. Although it’s not McDonald’s topic, his writing drove my thinking along another … Continue reading
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