Tag Archives: 32nm

By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley

There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading

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IBM to manufacture 32nm SOI chips with eDRAM in new GLOBALFOUNDRIES Fab 8 (Malta, NY)

IBM is the first announced customer for GLOBALFOUNDRIES’ Fab 8 in Malta, NY. The companies plan to manufacture IBM’s 32nm SOI devices at the site using an SOI process technology. The new plant has already been facilitized with more than … Continue reading

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How fast can an ARM Cortex-A15 run? 2GHz in Samsung’s 32nm process technology. That’s fast!

At the eighth annual Samsung Mobile Solutions Forum held at the Westin Taipei, Taiwan, Samsung previewed the Exynos 5250 applications processor, which is based on a dual-core implementation of the ARM Cortex-A15 processor running at 2GHz implemented in the company’s … Continue reading

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3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors

One more process node click, from 45nm to 32nm, bumped the clock rate of the Ambarella A7L SoC’s on-chip ARM 1136J-S RISC processor core to 600MHz from 528MHz. But reading the press release, I get the impression that the real … Continue reading

Posted in ARM, EDA360, Firmware, Low Power, Memory, Silicon Realization, SoC Realization, System Realization | Tagged , , , | Leave a comment

Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?

EDA companies like Cadence focus on developing the latest tools for bleeding-edge process technologies—28nm and 20nm today—and that’s been the emphasis of my blog posts from last week’s Global technology Conference (GTC). However, there was one panel at the conference … Continue reading

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Who else wants to see a 60x speedup in DFM signoff on a 28nm design?

Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES’ DRC+ methodology. This approach to DRC is interesting because it’s the industry’s first approach to DRC that teams … Continue reading

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Check your system-level design assumptions at the door

Jon McDonald’s opinion piece, just published in the System-Level Design Community section of Chip Design Magazine’s site, is about assumptions built into the design of complex electronic systems. Although it’s not McDonald’s topic, his writing drove my thinking along another … Continue reading

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