Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Download the EDA360 Vision Paper here:
Tag Archives: FPGA
Xilinx takes Zynq to 11—or more precisely to 1GHz
In the satirical 1984 movie “This is Spinal Tap,” Nigel the guitarist explains why the volume controls on his Marshall amps go to 11 instead of 10 like everyone else’s amps: “If we need that extra push over the cliff,” … Continue reading
Posted in Cortex-A9, EDA360
Tagged ARM Cortex-A9, ARM Cortex-A9 MPCore, FPGA, Xilinx, zynq 7000
Leave a comment
Innovate or die! A high-tech parable from this week’s Time Magazine
Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading
Posted in 2.5D, 20nm, 28nm, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged Android, BlackBerry, FPGA, iPhone, John Roberts, RIM
Leave a comment
Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can
Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading
Posted in 2.5D, 3D, EDA360, SoC, SoC Realization, System Realization
Tagged 2.5D, 28Gbps, Altera, FPGA, software, Virtex 7, Xilinx
Leave a comment
Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development
In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging … Continue reading
Amazing Friday Video: Xilinx GTZ SerDes transceivers pump 26Gbps/channel through Luxtera silicon photonics module
Setup for this video is pretty complicated so bear with me. The following video shows a Xilinx test chip with “7 Series GTX” transceivers pumping 26Gbps data over four channels through a stand-alone Luxtera “silicon optics” multichannel transceiver module. The … Continue reading
Software development for SoCs requires “bespoke” software enablement platforms
I’ve always wanted to use the British English word “bespoke” in a blog and Cadence Group Director of Product Marketing for the System Development Suite Frank Schirrmeister has now given me that opportunity with his EDPS forecast on system-level EDA … Continue reading
Posted in EDA360, System Realization
Tagged Android, FPGA, Google, iOS, iPad, iPhone, RTL, Software development kit
Leave a comment
3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?
I just posted a blog entry about the Altera Optical FPGA that pumped 100Gigabit/sec Ethernet (GbE) traffic through a 3D-package-on-package-mounted, 12-channel optical interconnect device from Avago. (See “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle … Continue reading
Posted in 3D, EDA360
Tagged 100 Gigabit Ethernet, Altera, Avago, Ethernet, FPGA, Gigabit Ethernet, Optical interconnect
Leave a comment
3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
This week at the Optical Fibre Communication Conference and Exposition (OFC) in Los Angeles, Altera demonstrated a specially modified Stratix IV FPGA that handled bidirectional 100Gbps Ethernet (100GbE) traffic over a pair of IC-package-mounted Avago MicroPOD multi-lane optical transceivers. The … Continue reading
Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization
Tagged Altera, Avago, Fiber Optics, FPGA, IBM, Molex
2 Comments
3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading
Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV
Tagged 2.5D, 2000T, FPGA, SerDes, Xilinx
2 Comments
3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading
Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
After the previous post on the announcement of the Altera SoC FPGA ran in EDA360 Insider—see “The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric”—I heard from people at Altera. They wanted … Continue reading
Posted in 28nm, ARM, Cortex-A9, EDA360, SoC Realization, System Realization
Tagged Altera, Altera SoC FPGA, FPGA, HPS, SoC FPGA
Leave a comment
How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
I met with Nandan Nayampally, Director of CPU Product Marketing for the Processor Division at ARM, at ARM TechCon 2011 last week and asked him for a short-form way of understanding the three major classes of 32-bit ARM Cortex processor … Continue reading
Posted in ARM, Cortex-A15, Cortex-A7, Cortex-A9, Silicon Realization, SoC, SoC Realization, System Realization
Tagged ARM Cortex, FPGA, Nvidia, Snapdragon, SPEAr1300, ST Microelectronics
Leave a comment
AppliedMicro demos FPGA emulation of multicore server chip based on new 64-bit ARMv8 architecture
OK, well that didn’t take very long at all. Minutes after ARM rolled out the 64-bit ARMv8 architecture announcement at ARM TechCon 2011, AMCC announced that it will be producing a multicore server chip dubbed “X-Gene” based on the new … Continue reading
Posted in ARM
Tagged Applied Micro Circuits Corporation, ARM architecture, ARM TechCon 2011, ARMv8, FPGA, Multicore
Leave a comment
3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Virtex, Xilinx
Leave a comment
Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Xilinx
Leave a comment
The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric
It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product … Continue reading
Posted in 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Altera, Cortex-A9, FPGA, Xilinx, Zynq
Leave a comment
3D Thursday: Do dis-integrated circuits reside in a 3D future? Does anyone (besides me) remember Project Tinkertoy?
I recently ran into this unusual article written by Joe Fjelstad and published on the Global SMT & Packaging Web site. The article discusses the possibility of building hybrid chips using a brick-and-mortar approach as advocated by a joint paper … Continue reading
Fire lasers! An EDA360, System Realization, and SoC Realization case study with military lasers, processors, and FPGAs
Robert S Grimes’ recently published development story is a good case study in System Realization and SoC Realization. Grimes developed a quad laser control system for a high-power military application and the article he’s published in EETimes—Designing with core-based high-density … Continue reading
6-Part series of blog posts on 28nm low-power design
Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization
Tagged 28nm, FPGA, Low Power, process technology, Xilinx
Leave a comment
Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
Leave a comment
Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Low Power, Xilinx
Leave a comment
Xilinx 28nm low-power SoC design class, part 4: Power gating RAMs
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, Xilinx
Leave a comment
Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, TSMC, Xilinx
Leave a comment
Xilinx 28nm low-power SoC design class, part 2: Process Technology
Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Field-programmable gate array, FPGA, TSMC, Xilinx
Leave a comment
3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!
Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization
Tagged 2.5D, 3D, FPGA, Xilinx
Leave a comment
EDA360 Insider 