3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, 36 12.5Gbps GTX serial transceivers, and 1200 user I/O pins. All in about 20W (!!!). The only fly in the ointment, if you want to call it that, is that no one on this planet can make this FPGA as a monolithic device. The Virtex-7 FPGA is a 2.5D assembly that combines four FPGA tiles on a silicon interposer.

Here’s an exploded diagram of the FPGA assembly:

The four active FPGA tiles are made by TSMC using its 28nm HPL (high-performance, low-power) high-K metal-gate (HKMG) process technology. TSMC also makes the silicon interposer, a massive 65nm IC in its own right, weighing in at 775 square millimeters. Although the silicon interposer for the Xilinx Virtex-7 2000T has no on-chip active elements, it still takes a multi-billion-dollar fab to make this piece of silicon. After the silicon pieces are fabricated at TSMC, Amkor provides the assembly expertise, combining the TSMC silicon with a package from IBIDEN.

The numbers on this FPGA are pretty impressive. Xilinx says that the two million logic gates are equivalent to about 20 million ASIC gates. Your mileage may well vary. However, there’s no question that there’s a lot of raw resource available on this device. At a live demo, Xilinx demonstrated 3600 8-bit picoBlaze soft processors running simultaneously on the Virtex-7  2000T FPGA. The processors in this demo were delivering 180,000 MIPS (180 GIPS) while the FPGA consumed just under 20W.

As Jedi Master Yoda would say: “Much power there is. Yes.”

Here’s a photo of the demo board:

The Xilinx 2.5D technology is really the star of the show here. Using this near-cousin to 3D assembly, Xilinx can push current-generation 28nm silicon to deliver the capabilities of the next process node without the yield problems associated with making such a big monolithic chip. As Xilinx Corporate VP for FPGA Development and Silicon Technology Liam Madden said, “It’s packaging’s turn in the industry.”

FPGAs naturally lend themselves to tiling; they have natural slice lines. They are inherently modular. So why aren’t the FPGA vendors already making tiled FPGAs? The reason becomes crystal clear when you look at the specs for the interposer used to connect four FPGA tiles in the Virtex-7 FPGA. The interposer makes 10,000 connections between each tile. That’s not a job for wire bonds. Even if you could put that many wire bonds down, they’d be electrically inadequate to the task due to their impedance.

Madden described the through-silicon vias used in the Xilinx interposer. Each via is 10 microns in diameter and 100 microns tall, which means the interposer is 100 microns thick, in case you were wondering. “The vias do not affect the signal integrity much at all” said Madden. The interconnects on the interposer are used to connect the long-line resources between the FPGA tiles. There is some extra delay associated with such huge long lines, but modifications made to the Xilinx place-and-route software and timing simulator to accommodate the extra delay apparently weren’t major.

The Xilinx Virtex-7 2000T FPGA represents a killer 3D app. It permits a generation jump in capabilities beyond what current monolithic IC manufacturing and lithography can produce. This application clearly demonstrates that 3D assembly is here to stay. And in case you think that somehow, 2.5D interposer-based assembly isn’t really 3D, take a look at this closeup of the interposer from the exploded image above:

Tell me you don’t think that silicon interposer is an IC in its own right. The absence of active on-chip elements may make it a different kind of IC, but you still need an IC fab to make one. Liam Madden said that he initially thought that 2.5D assembly was an interim solution. After managing the Virtex-7 2000T project, Liam said “I think 2.5D will have a life of its own.”


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , , , , . Bookmark the permalink.

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