Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- ARM unveils 64-bit v8 architecture at ARM TechCon 2011
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
Download the EDA360 Vision Paper here:
Tag Archives: Double Patterning
20nm design: What have we learned so far?
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence
The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading
Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Cadence, Double Patterning, Multiple patterning, Samsung, Webinar
Leave a comment
Looking at 20nm design? Three free Webinars can help.
With the 20nm click on the process technology dial staring us in the face, you might be wanting some informative, experience-based help. Three free Webinars taking place on May 1, 2, and 3 will give you some extra oomph in … Continue reading
Posted in 20nm, EDA360, Silicon Realization, TSMC
Tagged 20nm, Cadence, Double Patterning, TSMC
Leave a comment
What are the challenges of EUV lithography and the issues surrounding double patterning? CDNLive! presentation provides details.
Richard Goering has just published an excellent blog post on double patterning for 20nm and 14nm process geometries in his blog Industry Insights. The post is based on a paper presented by IBM Distinguished Engineer Lars Liebman at the recent … Continue reading
Posted in 14nm, 20nm, Double Patterning, EDA360, EUV, Silicon Realization
Tagged 20nm 14nm, Double Patterning, EUV, Extreme ultraviolet lithography, IBM, Lithography, Microprocessor Report
Leave a comment
By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading
Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, Double Patterning, Doubletree, GlobalFoundries, IBM, Samsung
Leave a comment
Just how high is the 20nm design mountain of challenges?
One of the last presentations at last week’s Global Technology Conference was the talk on 20nm design challenges presented by Wei Lii Tan of Cadence. Tan first summarized the benefits of the 20nm process node relative to 28nm: 30-50% better … Continue reading
Posted in ARM, EDA360, Globalfoundries, Silicon Realization, SoC Realization
Tagged Applied Materials, Double Patterning
Leave a comment
Friday Video: Everything you wanted to know about double patterning at 20nm and below…but were afraid to ask
Dr. Lars Liebman at IBM gave a very clear talk about the need for double patterning at the 22nm and 14nm nodes while at DAC a couple of months ago. Until EUV is ready for production, which is not expected … Continue reading
Posted in EDA360, Silicon Realization
Tagged 20nm, Double Patterning, IBM, IC lithography
Leave a comment
EDA360 Insider 