Tag Archives: DDR3

AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design

Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display … Continue reading

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Posted in 32nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

Who else wants to learn high-speed PCB design and signal integrity analysis from world-renown expert Robert Hanson—for FREE?

Do the words “high-speed PCB design” make you twitch uncontrollably? How about “signal integrity analysis”? “Crosstalk”? Perhaps the phrase “complex power-delivery networks” is your nemesis. All of these topics can be real bears to deal with when you are laying … Continue reading

Posted in EDA360, Packaging, pcb | Tagged , , , , , | 1 Comment

How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?

LeCroy introduced an upgrade to its Kibra 380 DDR3 SDRAM protocol analyzer today. The analyzer’s probes plug in series with the DDR3 SDRAM modules and the analyzer can identify more than 65 JEDEC command protocol and timing violations in real … Continue reading

Posted in EDA360, Silicon Realization, SoC Realization, System Realization, Verification | Tagged , , , , | Leave a comment

JEDEC releases more details about DDR4 SDRAM spec. Want to know what they are?

Although DDR3 memory is just ramping up in sales, JEDEC has been working on the next-generation DDR4 specification for faster SDRAM that consumes even less power. To achieve these goals, JEDEC announced yesterday that has specified the following key features … Continue reading

Posted in EDA360, Memory, SoC Realization | Tagged , , , | 1 Comment

Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?

Last week, I quoted Ann Steffora Mutschler’s article about the information that Micron has revealed about it’s 3D Hybrid Memory Cube. Now that I’ve got the paper Micron presented at last week’s Hot Chips 23 conference, I’d like to explain … Continue reading

Posted in 3D, EDA360, Packaging, Silicon Realization, TSV | Tagged , , , , | 2 Comments

Friday Video: What’s Next For Memory Designs In 2012? – from Agilent

Agilent has created a 6-part video series titled “What’s Next For Memory Designs In 2012?” that’s well worth a look. There’s about 30 minutes of video total, chopped into 2-8 minute pieces that you’ll want to watch if you have any … Continue reading

Posted in EDA360, Memory, Packaging, System Realization | Tagged , , , , | 1 Comment

Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee

I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading

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