Tag Archives: verification

Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence

On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading

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DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots

Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading

Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , | Leave a comment

FREE Webinar on analog verification. Wednesday, May 9 at 9:00 am PST

Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading

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There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?

There are a range of low-power design approaches for ASIC design including: Clock Gating Multi-Voltage Power Shutoff Dynamic Voltage Body Bias Adaptive Voltage All of the above Used in combination, there are more than 80,000 possible low-power modes that all … Continue reading

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10 questions to ask your verification IP (VIP) supplier

Last month, Richard Goering wrote an excellent blog post on “Best Practices for Selecting and Using Verification IP (VIP).” In this blog post, Richard listed ten questions you should make sure you can answer when selecting commercial VIP. The ten … Continue reading

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Friday Video: Incisive Formal Verifier solves Rubik’s Cube redux at DVCon 2012

You’ve seen robotic Rubik’s cube solvers before—even in EDA360 Insider. (For example, see “Friday Video: Multicore, ARM-powered CubeStormer II solved Rubik’s Cube puzzle in world-beating 4.762 seconds”). Well, Cadence once again had its robotic Rubik’s Cube solver powered by Incisive … Continue reading

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Do you know all of the essential aspects of VIP to make a good make/buy decision?

The growth of standards-based interfaces and the rapid advance in the state of the art for SoC design have created a real need for pro-quality verification IP (VIP). One interesting facet of VIP development is its parallel evolution with design … Continue reading

Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Verification, VIP | Tagged , , | 2 Comments

Free Webinar. Maximize the power of UVM runtime phases to avoid common verification pitfalls.

Verification expert Kathleen Meade has authored a methodology for applying UVM runtime phases that appears in the second edition of the Cadence UVM Book. On December 7, Kathleen will present a free verification Webinar covering the following topics: Basics of … Continue reading

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When is it OK to stop verifying your design? Free Webinar will tell you how to know when you’ve done enough

Verification takes a big chunk out of your development budget and one of the most difficult questions to answer about verification is: “When and how will I know if we’re done?” One word: “Metrics.” If you want to know when … Continue reading

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EDA360, verification, UVM, and the future of EDA standards

Adam Sherilog Sherer, the Cadence Incisive Product Management Director, just published a blog about his experience in calling on several existing customers to discuss UVM (The Universal Verification Methodology being developed under Accelera’s banner). (“We Want UVM 1.0! When Do … Continue reading

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