Tag Archives: FinFET

ARM, TSMC announce collaboration on FINfet-based ARM v8 processor core for sub-20nm SoC designs

Posted on July 23, 2012 by sleibson2

Today, ARM and TSMC announced a multi-year deal to develop a 64-bit ARM v8 processor “beyond” the 20nm node using FINfets. The collaboration includes the ARMv8 architecture, ARM Artisan physical IP, and TSMC’s FinFET process technology. The target of this … Continue reading →

Posted in 10nm, 14nm, 20nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , | Leave a comment

Friday Video: Luigi Capodieci, a fellow at GLOBALFOUNDRIES, talks 20nm and below, EUV, FINFETs, and the state of the foundry business

Posted on July 20, 2012 by sleibson2

Be sure to watch this excellent 13-minute interview done by Mark LePedus starring Luigi Capodieci, a fellow with GLOBALFOUNDRIES, to get a close-up-and-personal look at the state of the foundry business (it’s not dying), 20nm design, EUV in the wings, … Continue reading →

Posted in 14nm, 20nm, EUV, Globalfoundries, Silicon Realization | Tagged , , | Leave a comment

3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design

Posted on June 7, 2012 by sleibson2

Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading →

Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

Professor Chenming Hu talks FinFETs and FDSOI at the GSA Silicon Summit

Posted on April 26, 2012 by sleibson2

Chenming Hu, TSMC Distinguished Chair Professor of Microelectronics at University of California at Berkeley gave a keynote talk on FinFETs and FDSOI (fully depleted silicon on insulator) today at the GSA Silicon Summit held at the Computer History Museum in … Continue reading →

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Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

Posted on March 22, 2012 by sleibson2

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading →

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment

GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley

Posted on February 7, 2012 by sleibson2

The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading →

Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | 1 Comment

GLOBALFOUNDRIES talks FinFETs, EUV, 14nm, ETSOI. Any other bleeding-edge chipmaking terms you wanted to hear?

Posted on September 5, 2011 by sleibson2

Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm … Continue reading →

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Friday Video: Intel does 22nm, 3D, and humor in one video. Who knew they had it in them?

Posted on August 5, 2011 by sleibson2
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David Manners writes about ARM versus Intel in the FinFET wars

Posted on August 1, 2011 by sleibson2

We like nothing more in this industry than a good fight. It drives a lot of discussion. If you can’t get your fill, zip on over to David Manner’s blog “ARM Unfazed by Finfets” to get an up-to-the-minute discussion of … Continue reading →

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3D Thursday: Daniel Nenni writes about Intel FinFETs

Posted on July 21, 2011 by sleibson2

FinFETs are hot this week (no pun intended). Ron Wilson published an article about FinFETs on the EETimes Web site and Daniel Nenni has done the same on his SemiWiki.com site. It’s worthwhile reading, particularly for insights such as these … Continue reading →

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3D Thursday: More words on the Intel FinFETs (this time from Ron Wilson at EETimes)

Posted on July 21, 2011 by sleibson2

Last month, I wrote a couple of articles on FinFETs, those 3D structures coming to some 20nm chips soon to be near you—like in your PC. See “Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part … Continue reading →

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Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 2)

Posted on June 20, 2011 by sleibson2

Yesterday’s blog entry discussed FinFETs as a way to build advanced-process transistors with reduced leakage and improved performance. (See “Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 1)“.) There’s another way to eliminate the unwanted … Continue reading →

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Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu

Posted on June 19, 2011 by sleibson2

Intel announced in early May that it would be using “Tri-Gate” FETs to build microprocessors at the 22nm node. (See the previous EDA360 Insider post “3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D”). Intel’s Tri-Gate transistor structures … Continue reading →

Posted in EDA360, Low Power, Silicon Realization | Tagged , , , , | 3 Comments

3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D

Posted on May 19, 2011 by sleibson2

Earlier this month, Intel announced that it will be using Tri-Gate transistors (FinFETs) to build microprocessors at the 22nm process node. The microprocessor is code-named “Ivy Bridge.” It will be a 22nm version of the company’s Sandy Bridge processor and … Continue reading →

Posted in 3D, EDA360, Low Power, Silicon Realization, SoC Realization | Tagged , , , , , , | 3 Comments